1. Field of the Invention
The present invention relates to a solid-state imaging apparatus and an imaging system.
2. Description of the Related Art
In recent years, CMOS image sensors are being widely used in digital cameras, digital camcorders, and camera units for mobile telephones. In response to demands to reduce the number of components and the power consumption, CMOS image sensors that have a built-in analog to digital (AD) conversion unit have been developed. One form of such kind of CMOS image sensor is referred to as a “ramp-type column ADC”. In a ramp-type column ADC, an AD conversion unit (ADC) is provided for each column of a pixel array. The ramp-type column ADC includes a comparator circuit and a reference signal generation circuit that are provided for each column. In many cases, the comparator circuit compares a pixel signal and a ramp signal that serves as a reference signal, measures a time period until the magnitude relationship between the potential of the pixel signal and the potential of the ramp signal inverts, and holds the measured time period as digital data in a column memory that is provided for each column. For example, Japanese Patent Application Laid-Open No. 2013-93837 discloses a method that outputs a count signal to respective column circuits by using a reference signal and a single counter that is referred to as a so-called “common counter” that counts a time period from a time point that the voltage of the reference signal starts to change from an initial voltage.
However, in the configuration disclosed in Japanese Patent Application Laid-Open No. 2013-93837, an N memory that holds a result obtained by performing AD conversion of a signal corresponding to resetting of a pixel, and an S memory that holds a result obtained by performing AD conversion of a signal corresponding to incident light from a pixel are physically separate circuits. Consequently, propagation delays until a count signal and a comparison result signal reach the N memory and the S memory, respectively, cannot be made completely equal. Furthermore, because the N memory and the S memory are separate circuits, differences can arise in latch circuit timings due to variations among transistor elements between the N memory and the S memory. That is, count values held in the N memory and the S memory differ due to the above described two factors. Consequently, signal components after CDS (correlated double sampling) processing include offsets and do not become 0. Because the offsets have a specific variation for each column, there is a possibility that the offsets will become noise components that deteriorate the image quality.
An object of the present invention is to provide a solid-state imaging apparatus and an imaging system that can reduce offsets that are noise components.